Semiconductor memory device adopting improved local input/output line precharging scheme

ABSTRACT

A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal, and a local input/output line precharging unit to precharge the pair of local input/output lines by a first precharging unit, equalizing the pair of local input/output lines by an equalizing unit, and to precharge the local input/output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated.

PRIORITY STATEMENT

This U.S. non-provisional patent application claims Priority Under 356U.S.C. §119 to Korean Patent Application 10-2008-0129775, filed on Dec.19, 2008, in the Korean Intellectual Property Office (KIPO), the entirecontents of which are incorporated herein by reference.

BACKGROUND

1. Field

Example embodiments of the present invention relate to a semiconductormemory device, and in particular, to a read data path circuit for use ina semiconductor integrated circuit device such as a dynamic randomaccess memory.

2. Description of the Related Art

There is a movement towards developing semiconductor memory devicesincluding dynamic random access memories (hereinafter, referred to asDRAMs) with a high degree of integration and high speed. DRAMs havememory cells and are generally adopted as main memories for electronicsystems. Each of the memory cells includes one access transistor and onestorage capacitor

Referring to FIG. 1, in a general data processing system, a DRAM 10adopted as a main memory is connected to a micro processing unit 2through a system bus B1. The micro processing unit 2 is connected to aflash memory 4 through a system bus B5, performs a processing operationset in accordance with a program stored in the flash memory 4, andcontrols a drive unit 6 through a control bus B2 as occasion demands. Inorder to perform a processing operation for controlling the drive unit6, the micro processing unit 2 performs a data accessing operation towrite data in memory cells of the DRAM 10 and read data from memorycells.

During a read operation, data stored in memory cells of the DRAM 10 aretransmitted to pairs of bit lines and are sensed and amplified by bitline sense amplifiers (hereinafter, referred to as BLSAs). Then, when acolumn selection line signal is activated, the data is transmitted topairs of local input/output lines. Sequentially, the data is provided todata output buffers through corresponding global input/output lines andthen output to the external of the semiconductor memory device.

In the DRAM 10, bit lines and local input/output lines which are notinvolved in the read operation are generally precharged to a voltage soas to increase a sensing speed and to prevent them from being floated.Pairs of local input/output lines are precharged to a voltage whichcorresponds to half of a source voltage or an operation voltage of amemory cell array. In other words, pairs of local input/output lines areprecharged to a voltage equal to a precharge voltage for the bit lines.The operation voltage of the memory cell array generally is slightlyless than or equal to the source voltage.

If a pair of local input/output lines are connected to localinput/output line sense amplifiers, in order to increase the sensingspeed of the local input/output line sense amplifiers, a technique forvarying a precharge voltage for a pair of local input/output lines inaccordance with an operation mode is applicable. For example, when apair of local input/output lines are maximally amplified to have theoperation voltage and a ground voltage, and are precharged to a firstvoltage, the precharging of the pair of local input/output lines maycause noise to change the level of the first voltage. In other words,the noise may influence a circuit which generates the first voltage,resulting in a drop in efficiency in sensing data from memory cells. Inthis case, the above-mentioned precharging technique may be applicable.

Until an active mode, for example, a read or write operation on memorycells starts, the pair of local input/output lines are precharged to thevoltage equal to the precharge voltage for the bit lines. When a wordline is enabled to enter an active mode, the pair of local input/outputlines are precharged to a voltage equal to the operation voltage of thecell array. When the active mode is ended, the pair of localinput/output lines are precharged to the voltage equal to the prechargevoltage for the bit lines again.

A general precharging circuit to precharge a pair of local input/outputlines in an active mode may not exhibit a satisfactory operation qualityboth under a short /RAS to /CAS delay time (hereinafter, referred to asa tRCD) condition and under a long tRCD condition. In other words, theprecharging circuit may exhibit a satisfactory operation quality eitherunder the short tRCD condition or the long tRCD condition. If theprecharging circuit does not exhibit a satisfactory operation qualityunder the short tRCD condition, a bit line disturbance phenomenon mayoccur, and if the precharging circuit does not exhibit a satisfactoryoperation quality under the long tRCD condition, a low-voltagehigh-speed operation quality may be degraded.

For this reason, a technique for realizing a low-voltage high-speedoperation while reducing or minimizing bit line disturbance is requiredto vary a precharging scheme in accordance with an operation mode toprecharge local input/output lines in a read data path circuit of a DRAMwhich applies data read from memory cells to output buffers in a readoperation.

SUMMARY

Example embodiments provide a semiconductor memory device capable ofperforming a precharging operation on local input/output lines bothunder a short tRCD condition and under a long tRCD condition. Thesemiconductor memory device may include a read data path circuit toperform a read operation at a lower voltage at a higher speed and toreduce or minimize bit line disturbance.

Example embodiments provide a local input/output line precharging schemefor a high-speed semiconductor memory device, which makes it possible toperform a read operation with a lower-voltage at a higher speed and toreduce or minimize bit line disturbance.

Example embodiments provide a local input/output line prechargingcircuit which performs NMOS charging under a short tRCD condition andPMOS precharging under a long tRCD.

Example embodiments provide a DRAM capable of flexibly controlling adesign margin for local input/output line sense amplifiers.

According to an example embodiment, a read data path circuit of asemiconductor memory device may include a bit line sense amplifier, alocal input/output line sense amplifier, a column selecting unitconfigured to operationally connect bit lines connected to the bit linesense amplifier to local input/output lines connected to the localinput/output line sense amplifier in response to a column selectionsignal and a local input/output line precharging unit.

The local input/output line precharging unit may be configured toprecharge the pair of local input/output lines by a first conductivetype precharging unit, to equalize the pair of local input/output linesby a second conductive type equalizing unit, and to precharge the pairof local input/output lines by a second conductive type precharging unitfollowing an elapsed time after the bit line sense amplifier isactivated, while the column selection is deactivated.

In the read data path circuit having the above-mentioned configuration,the first conductive type precharging unit of the local input/outputline precharging unit may include two NMOS transistors, and the secondconductive type equalizing unit of the local input/output lineprecharging unit may include one PMOS transistor. Moreover, the secondconductive type precharging unit of the local input/output lineprecharging unit may include two PMOS transistors.

According to another example embodiment, a semiconductor memory devicemay include a memory cell array including a plurality of memory cellsarranged in a matrix, each of the plurality of memory cells may includeone access transistor and one storage capacitor, a plurality of bit linesense amplifiers may be connected to corresponding bit lines connectedto the plurality of memory cells, a plurality of local input/output linesense amplifiers may each be connected to a corresponding globalinput/output line sense amplifier through corresponding globalinput/output lines, a plurality of column selecting units each of whichmay be configured to operationally connect corresponding bit lines to acorresponding pair of local input/output lines connected to acorresponding local input/output line sense amplifier, in response to acolumn selection signal and a plurality of local input/output lineprecharging units.

Each of the local input/output line precharging units may be configuredto precharge corresponding local input/output lines by a firstconductive type precharging unit, to equalize the corresponding localinput/output lines by a second conductive type equalizing unit, and toprecharge the corresponding pair of local input/output lines by a secondconductive type precharging unit following an elapsed time after acorresponding bit line sense amplifier is activated, while the columnselection signal input to a corresponding column selecting unit isdeactivated.

In the semiconductor memory device having the above-mentionedconfiguration, when the first conductive type precharging unit includesNMOS transistors, the second conductive type precharging unit mayinclude PMOS transistors.

The semiconductor memory device may further include a plurality of halfsource voltage precharging/equalizing units configured to prechargecorresponding local input/output lines to a voltage equal to half of asource voltage until a corresponding word line is activated.

Each of the half source voltage precharging/equalizing units may includeNMOS transistors.

According to an example embodiment, a read data path circuit of asemiconductor memory device may include a bit line sense amplifier, alocal input/output line sense amplifier, a column selecting unit may beconfigured to operationally connect bit lines connected to the bit linesense amplifier to local input/output lines connected to the localinput/output line sense amplifier, in response to a column selectionsignal and a local input/output line precharging unit.

The local input/output precharging unit may be configured to prechargethe local input/output lines by NMOS transistors, to equalize the localinput/output lines by a PMOS transistor, and to precharge the localinput/output lines by PMOS transistors after an elapsed time after thebit line sense amplifier is activated, in response to an active commandwhile the column selection signal is deactivated.

In the read data path circuit having the above-mentioned configuration,the local input/output line precharging unit may include a delay unitdelaying a bit line sense amplifier enable signal for a set time; and aNAND gate performing a NAND operation on an output of the delay unit andan equalization enable signal of the PMOS transistor for equalizing, toproduce a NAND response in order to activate the second conductive typeprecharging unit.

According to example embodiments, bit line disturbance may be minimizedor reduced and a read operation is performed at a lower voltage and at ahigher speed. Moreover, the NMOS precharging may be performed under theshort tRCD condition and the PMOS precharging is performed under thelong tRCD condition. Therefore, the example embodiments may be robustagainst bit line disturbance and are advantageous for a low-voltagehigh-speed operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.FIGS. 1-9 represent non-limiting, example embodiments as describedherein.

FIG. 1 is a block diagram illustrating a configuration of a general dataprocessing system.

FIG. 2 is a diagram illustrating a read data path circuit using a localinput/output line precharging scheme according to the related art.

FIG. 3 is a diagram illustrating a read data path circuit using a localinput/output line precharging scheme according to the related art.

FIG. 4 is a diagram illustrating a read data path circuit using a localinput/output line precharging scheme according to an example embodiment.

FIG. 5 is a diagram illustrating conjunction areas of a semiconductormemory device where some of circuit elements of FIG. 4 are located.

FIG. 6 is a diagram illustrating an example configuration of a localinput/output line sense amplifier of FIG. 4.

FIG. 7 is a diagram illustrating an example configuration of anequalization signal generating unit involved in a local input/outputline equalizing operation of the circuit of FIG. 4.

FIG. 8 is a timing chart illustrating a local input/output lineprecharging operation of the circuit of FIG. 4.

FIG. 9 is a waveform chart illustrating simulation results for comparinga case of using the local input/output line precharging unit shown inFIG. 4 as compared to using a local input/output line precharging unitaccording to the related art.

It should be noted that these Figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feat.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference tothe accompanying drawings. In the drawings, the thicknesses of layersand regions may be exaggerated for clarity.

Specific structural and functional details disclosed herein are merelyrepresentative for purposes of describing example embodiments. Exampleembodiments may, however, may be embodied in many alternate forms andshould not be construed as limited to only the embodiments set forthherein.

Accordingly, while example embodiments are capable of variousmodifications and alternative forms, embodiments thereof are shown byway of example in the drawings and will herein be described in detail.It should be understood, however, that there is no intent to limitexample embodiments to the particular forms disclosed, but on thecontrary, example embodiments are to cover all modifications,equivalents, and alternatives falling within the scope of exampleembodiments. Like numbers refer to like elements throughout thedescription of the figures.

It will be understood that, although the terms first, second and thirdmay be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like may be used herein for ease of description todescribe the relationship of one component and/or feature to anothercomponent and/or feature, or other component(s) and/or feature(s), asillustrated in the drawings. It will be understood that the spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising,”, “includes” and/or “including”, when usedherein, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andshould not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 2 is a diagram illustrating a read data path circuit using a localinput/output line precharging scheme according to the related art. Indescribing FIG. 2, plurality of will be used in it's broadest sense andmay include one, one or more, or many elements.

Referring to FIG. 2, a read data path circuit of a DRAM includes amemory cell array 11, a plurality of bit line sense amplifiers 13, aplurality of column selecting units 15, a plurality of localinput/output line precharging/equalizing units 17, a plurality of localinput/output line sense amplifiers 19, a plurality of globalinput/output line sense amplifiers 21, and a plurality of output buffers23.

The memory cell array 11 includes a plurality of memory cells which eachhave one access transistor AT and one storage capacitor SC. Word lines(e.g., word lines WL1 and WL2) may be connected to gates of accesstransistors AT of corresponding memory cells. Bit lines BL may be pairedwith complementary bit lines BLB, and the pairs of bit lines may beconnected to drain/sources of corresponding access transistors AT. Eachpair of bit lines may be connected to a corresponding bit line senseamplifier 13.

The bit line sense amplifier may include a PMOS sense amplifier PSAhaving PMOS transistors P1 and P2. The PMOS sense amplifier PSA may havean enable signal LAPG. The bit line sense amplifier may include a NMOSsense amplifier NSA having NMOS transistors N1 and N2. The NMOS senseamplifier NSA may have an enable signal LANG.

In a read operation, data stored in selected memory cells may appear asa potential difference on a corresponding pair of bit lines which may besensed and amplified by a corresponding bit line sense amplifier 13.

Each column selecting unit 15 may include column selecting transistorsQ1 and Q2 that may operationally connect a pair of bit lines BL and BLBto a pair of local input/output lines LIO and LIOB connected to acorresponding local input/output line sense amplifier 19, in response toa column selection signal CSL. Accordingly, in a read operation, sensedand amplified data on the pair of bit lines may be transmitted to thepair of local input/output lines LIO and LIOB.

Before a word line is activated to perform a read or write operation onselected memory cells, a half source voltage precharging/equalizing unit17 b may precharge a pair of local input/output lines LIO and LIOBcorresponding to the selected memory cells to a first voltagecorresponding to the precharge voltage for bit lines or half of a sourcevoltage. To this end, a high-level control signal CON2 may be applied togates of NMOS transistors NM1, NM2, and NM3 of the half source voltageprecharging/equalizing unit 17 b and a voltage V1 equal to the prechargevoltage VBL for bit lines, for example, half of the source voltage maybe applied to a common drain node of the NMOS transistors NM1 and NM2.

A local input/output line precharging unit 17 a of the localinput/output line precharging/equalizing unit 17 may precharge the pairof local input/output lines LIO and LIOB to a second voltage equal to anoperation voltage of the memory cell array during a period when a wordline is in an active state and a column selection signal CSL is in aninactive state in an active mode.

A control signal CON1 having a high level may be applied to gates ofPMOS transistors PM1, PM2, and PM3 of the local input/output lineprecharging unit 17 a when the word line is in an active state, and avoltage V2 equal to the operation voltage of the memory cell array maybe applied to a common source node of the PMOS transistors PM1 and PM2.The PMOS transistors PM1 and PM2 may be involved in a prechargingoperation and the PMOS transistor PM3 may be involved in an equalizingoperation.

In a read operation, the local input/output line sense amplifier 19 maysense read data having been transmitted from the memory cells onto thepair of local input/output lines LIO and LIOB, may amplify the readdata, and may output the read data to a pair of global input/outputlines GIO and GIOB. The global input/output line sense amplifier 21 maysense the read data on the pair of global input/output lines GIO andGIOB, and may amplify the read data, and may output the read data to anoutput buffer 23.

In the read data path circuit as shown in FIG. 2, aprecharging/equalizing operation by the PMOS transistors of the localinput/output line precharging unit 17 a may cause bit line disturbance.

If a precharging/equalizing operation by the PMOS transistors PM1, PM2,and PM3 is performed to make the pair of local input/output lines havethe second voltage equal to the operation voltage of the memory cellarray, if the column selection signal CSL is enabled under a short tRCDcondition in which the bit line sense amplifier 13 have not yetsufficiently developed the pair of local input/output lines, a bit linedisturbance phenomenon may occur.

For example, when a state in which there is no charge stored in a memorycell is defined as logical data “0” and a state in which there is chargestored in a memory cell is defined as logical data “1”, if logical dataof a selected memory cell is “0”, an electric potential of a bit line BLof a pair of bit lines, which is lower than an electric potential of acorresponding complementary bit line BLB, is sensed and amplified by abit line sense amplifier 13, and is transmitted to a local input/outputline LIO of a pair of local input/output lines LIO and LIOB through acolumn selecting transistor Q2 of the column selecting unit 15. Duringan early period of a sensing operation of the local input/output linesense amplifier 19 after the column selection signal CSL is activated,an electric potential difference between the pair of bit lines BL andBLB may not be sufficient.

Therefore, electric charge precharged on the local input/output line LIOmay raise the electric potential of the bit line BL through the columnselecting transistor Q2. If the electric potential of the bit line BLrises, the electric potential difference between the pair of bit linesBL and BLB decreases. This phenomenon is referred to as bit linedisturbance.

If a mismatch of the bit line sense amplifiers occurs during an earlyperiod of a sensing operation, the bit line disturbance phenomenon inwhich electric charge on one of a pair of local input/output lines istransferred to one of a pair of bit lines having a lower electricpotential may cause reverse sensing.

Degradation in a low-voltage high-speed operation quality due to aprecharging operation of NMOS transistors NM10 and NM11 and anequalizing operation of a PMOS transistor PM1 in a local input/outputline precharging unit 17 a-1 will be described with reference to FIG. 3.FIG. 3 and FIG. 4 contain like elements to FIG. 1. Only elements havingdiffering features will be described further with regards to FIG. 3 andFIG. 4.

A precharging operation of the NMOS transistors NM10 and NM11 and anequalizing operation of the PMOS transistor PM1 may make a localinput/output line LIO have a voltage which is equal to a voltageobtained by subtracting a threshold voltage Vth of the NMOS transistorsNM10 and NM11 from an operation voltage of a memory cell array.Therefore, the circuit of FIG. 3 may exhibit an improved quality under ashort tRCD condition, as compared to the circuit of FIG. 2. However, ina low-voltage high-speed operation, a deterioration in an equalizingquality may occur due to a drop in a gate-to-source voltage of the PMOStransistor PM1.

In order to prevent or minimize bit line disturbance and to prevent orminimize a deterioration in a low-voltage high-speed operation quality,an example embodiment provides a local input/output line prechargingunit 100 as shown in FIG. 4.

Referring to FIG. 4, if a column selection signal CSL is in an inactivestate, the local input/output line precharging unit 100 may primarilyprecharge a pair of local input/output lines LIO and LIOB by NMOStransistors NM10 and NM11 and perform an equalizing operation by a PMOStransistor PM3. If a set time elapses after a bit line sense amplifier13 is activated, the local input/output line precharging unit 100 maysecondarily precharge the pair of local input/output lines LIO and LIOBby PMOS transistors PM1 and PM2.

The local input/output line precharging unit 100 may include a delayunit DE1, a NAND gate NA1, and an inverter I1. The delay unit DE1 mayreceive a bit line sense amplifier enable signal SAEN and delays the bitline sense amplifier enable signal SAEN for a set time. The NAND gateNA1 may perform a NAND operation on the bit line sense amplifier enablesignal SAEN from the delay unit DE1 and a high-level control signal CON1applied if a word line is in an active state and the column selectionsignal is in an inactive state in an active mode, thereby producing aNAND response. The inverter I1 may invert the control signal CON1 andmay apply the control signal CON1 to a gate terminal of the PMOStransistor PM3.

The local input/output line precharging unit 100 of FIG. 4 may performNMOS precharging under a short tRCD condition and performs PMOSprecharging under a long tRCD condition. Therefore, the localinput/output line precharging unit 100 may be robust against bit linedisturbance and advantageous for a low-voltage high-speed operation.

FIG. 4 is a diagram illustrating a read data path circuit using a localinput/output line precharging scheme according to an example embodiment.

FIG. 5 is a diagram illustrating conjunction areas of a semiconductormemory device where some circuit elements of FIG. 4 are located. FIG. 6is a diagram illustrating an example configuration of a localinput/output line sense amplifier of FIG. 4. FIG. 7 is a diagramillustrating an example configuration of an equalization signalgenerating unit involved in a local input/output line equalizingoperation of the circuit of FIG. 4.

FIG. 8 is a timing chart illustrating a local input/output lineprecharging operation of the circuit of FIG. 4. FIG. 9 is a waveformchart illustrating simulation results comparing using the localinput/output line precharging unit shown in FIG. 4 and using a localinput/output line precharging unit according to the related art.

Referring to FIG. 4, a memory cell array 11, a bit line sense amplifier13, a column selecting unit 15, a half source voltageprecharging/equalizing unit 17 b, a local input/output line senseamplifier 19, a global input/output line sense amplifier 21, and anoutput buffer 23 may have the same configurations as those in FIGS. 2and 3.

A word line is activated to perform a read or write operation on memorycells, the half source voltage precharging/equalizing unit 17 bprecharges a pair of local input/output lines LIO and LIOB to a voltagecorresponding to the precharge voltage VBL for bit lines or half of asource voltage. When the word line is in an inactive state, a high-levelcontrol signal CON2 may be applied to gates of NMOS transistors NM1,NM2, and NM3 of the half source voltage precharging/equalizing unit 17 band a voltage V1 equal to the precharge voltage VBL for bit lines orhalf of the source voltage may be applied to a common drain node of theNMOS transistors NM1 and NM2. Such a precharging operation is performedduring periods T1 and T3 of FIG. 8.

Referring to FIG. 8, in the period T1, the control signal CON2 may havethe high level and the control signal CON1 may have the low level.Further, the column selection signal CSL may maintain an inactive state.

If the period T1 ends, in order to read data from memory cells, anactive mode in which a word line WL connected to the memory cells may beactivated.

In FIG. 8, if an active mode signal ACT is at a high level, the columnselection signal CSL may be periodically transitioned between the highlevel and the low level as shown in FIGS. 8 and 9, the control signalCON2 may have a low level, and the control signal CON1 may beperiodically transitioned between a high level and a low level to have alevel opposite to the level of the column selection signal CSL. Anequalization signal generating circuit 150 of FIG. 7 may generate alocal input/output line equalization signal LIOEQ having a waveform asshown in FIG. 8. In the period T2, a precharging operation may beperformed to precharge the pair of local input/output lines to a voltageequal to the operation voltage VINTA of the memory cell array.

If a word line is in an active state and the column selection signal CSLis in an inactive state, the local input/output line precharging unit100 may precharge the pair of local input/output lines LIO and LIOB to avoltage equal to the operation voltage of the memory cell array over twostages.

The local input/output line precharging unit 100 may primarily prechargethe pair of local input/output lines LIO and LIOB by NMOS transistorsNM10 and NM11 and equalizes the pair of local input/output lines LIO andLIOB by a PMOS transistor PM3. When a set time elapses after the bitline sense amplifier 13 is activated, the local input/output lineprecharging unit 100 may secondarily precharge the pair of localinput/output lines LIO and LIOB by PMOS transistors PM1 and PM2.

As described above, under a short tRCD condition, NMOS precharging maybe performed to make the pair of local input/output lines LIO and LIOBhave a voltage equal to a voltage obtained by subtracting a thresholdvoltage Vth of the NMOS transistors NM10 and NM11 from an operationvoltage of a memory cell array, and under a long tRCD condition, PMOScharging may be performed to make the pair of local input/output linesLIO and LIOB have a voltage equal to the operation voltage of the memorycell array. Accordingly, the read data path circuit may be robustagainst bit line disturbance and advantageous for a low-voltagehigh-speed operation.

The operation to precharge the pair of local input/output lines LIO andLIOB to the voltage equal to the operation voltage of the memory cellarray may continue until the word line is disabled to finish the activemode. The precharging operation on the pair of local input/output linesLIO and LIOB may be interrupted when data is transmitted to the pair oflocal input/output lines LIO and LIOB through a pair of bit lines BL andBLB. If a column address strobe signal is applied and the columnselection signal CSL is enabled, column selecting transistors Q1 and Q2may be turned on to connect the pair of bit lines BL and BLB to the pairof local input/output lines LIO and LIOB.

If the column selecting transistors Q1 and Q2 are in an ON state, aprecharging operation on the pair of local input/output lines LIO andLIOB may not be performed. A voltage corresponding to data may besupplied to the pair of local input/output lines LIO and LIOB and aprecharge enable signal PRECHR may be disabled as shown in FIG. 8. Ifthe active mode finishes and the period T3 starts, the pair of localinput/output lines LIO and LIOB may be precharged to a voltage equal tothe precharge voltage for the bit lines.

As shown in FIG. 7, the equalization signal generating unit 150 maygenerate the local input/output line equalization signal LIOEQ on thebasis of a combination of the active mode signal ACT and the columnselection signal CSL. The term “active mode” may define an operationmode from when a word line WL connected to selected memory cells isenabled to when the word line WL is disabled. Accordingly, the term“active mode signal” may define a word line enable signal WL.

The equalization signal generating unit 150 may include an AND gateA110, NOR gates NO110 and NO112, and inverters I110 and I112 which maybe connected as shown in FIG. 7. The equalization signal generating unit150 may generate the local input/output line equalization signal LIOEQhaving an enable period (the period T2 in FIG. 8) from when the columnselection signal CSL is enabled for the first time in the active mode towhen the active mode finishes.

The inverter I11 of FIG. 4 may be within conjunction areas AR1 and AR3shown in FIG. 5, and the delay unit DE1 may be within a peripheral areaof the whole area of FIG. 5.

FIG. 5 illustrates conjunction areas of a semiconductor memory devicewhere the inverter I1 of FIG. 4 may be located. In FIG. 5, sub word linedriver areas AR4 and bit line sense amplifier areas AR2 may be aroundmemory cell blocks of a memory cell array MCA and the conjunction areasAR1 and AR3 may be at intersections of the sub word line driver SWDareas AR4 and the bit line sense amplifier areas AR2. Drivers such asthe inverter I1 may be in the conjunction areas AR1 and AR3.

In some example embodiments, the inverter may be designed in theconjunction area AR1 and AR3 and the delay unit and various trimmingcircuits for controlling an amount of delay of the delay unit may bedesigned in the peripheral area, resulting in a sufficient layoutmargin. Trimming is achieved by applying a test mode register set signalor a fuse option.

FIG. 6 illustrates an example configuration of the local input/outputline sense amplifier 19 of FIG. 4. Referring to FIG. 6, the localinput/output line sense amplifier 19 may include NMOS transistors 201 to205. A sense amplifier enable signal PLSAE may be input to the localinput/output line sense amplifier 19. If the sense amplifier enablesignal PLSAE is transitioned to a high level, the local input/outputline sense amplifier 19 may be activated, senses and amplifies dataappearing on the pair of local input/output lines LIO and LIOB, andtransmits the data to a pair of global input/output lines GIO and GIOB.

FIG. 9 is a waveform chart illustrating the results of a simulation forcomparing using the local input/output line precharging unit shown inFIG. 4 and using a local input/output line precharging unit according tothe related art.

The simulation was performed on the assumption that a source voltage is1.1 V and a DDR clock frequency is 2133 Mbps. In FIG. 9, a horizontalaxis represents time in nanoseconds and a vertical axis representsvoltage in volts.

The first graph CA from the top of FIG. 9 represents electric potentialdevelopment between a pair of local input/output lines when NMOSprecharging is performed according to the related art. Reference symbolsS1 and S2 represent profiles of precharge voltages of the pair of localinput/output lines during a period when the column selection signal CSLis in an inactive state. The profiles S1 and S2 that the levels of theprofiles S1 and S2 are lowered as time elapses, for example, as the tRCDgets longer, and the pair of local input/output lines are notsatisfactorily equalized.

The second graph PI from the top of FIG. 9 may represent electricpotential development between a pair of local input/output lines ifprecharging is performed according to the exemplary embodiment of FIG.4. The profiles S1 and S2 of precharge voltages of the pair of localinput/output lines that the levels of the profiles are not lowered overtime and the pair of local input/output lines may be satisfactorilyequalized.

The third and fourth graphs WA1 and WA2 from the top of FIG. 9 representoutputs of the NAND gate NA1 and the inverter I1 of FIG. 4.

The fifth graph from the top of FIG. 9 may represent a sensing margin ofthe circuit of FIG. 4 and a sensing margin of the circuit of FIG. 2. Inthe circuit of FIG. 2 according to the related art, the sensing marginat input terminals of the global input/output line sense amplifier 21 is120 mV, and the circuit of FIG. 4 according to the example embodiment,the sensing margin at input terminals of the global input/output linesense amplifier 21 is 400 mV. The sensing margin according to theexample embodiment may be improved as compared to that according to therelated art. As described above, example embodiments may have noticeableeffects as compared to the related art.

The five consecutive pulses of the fifth graph of the FIG. 9 representsa burst read operation.

In the drawings and specification, there have been disclosed embodimentsof the invention and, although specific terms are employed, they areused in a generic and descriptive sense only and not for limitation.While the inventive concepts have been particularly shown and describedwith reference to exemplary embodiments, it will be understood thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the invention, as described bythe following claims. For example, the delay of the delay unit, theinternal connection of the precharging unit, and others can be changed.Moreover, exemplary embodiment of the invention is applicable tovolatile memories such as pseudo SRAMs as well as DRAMs.

While example embodiments have been particularly shown and described, itwill be understood by one of ordinary skill in the art that variationsin form and detail may be made therein without departing from the spiritand scope of the claims.

1. A read data path circuit of a semiconductor memory device, thecircuit comprising: a first sense amplifier; and a precharging unitincluding a first conductive type precharging unit, a second conductivetype precharging unit and an equalizing unit, the first conductive typeprecharging unit configured to precharge input/output lines, theequalizing unit configured to equalize a voltage of the input/outputlines of the circuit, the second conductive type precharging unitconfigured to precharge the input/output lines following an elapsed timeafter the first sense amplifier is activated and while a columnselection unit is deactivated.
 2. The read data path circuit of claim 1,wherein the column selecting unit is configured to operationally connectbit lines corresponding with the first sense amplifier to theinput/output lines in response to a selection signal, and theinput/output lines corresponding with a second sense amplifier.
 3. Theread data path circuit of claim 2, wherein the precharging unit furtherincludes, a delay unit configured to delay an enable signal to thesecond sense amplifier; and a NAND gate performing a NAND operation onan output of the delay unit and an equalization enable signal of theequalizing unit, to produce a NAND response in order to activate thesecond conductive type precharging unit.
 4. The read data path circuitof claim 1, wherein the first conductive type precharging unit includestwo NMOS transistors.
 5. The read data path circuit of claim 4, whereinthe equalizing unit includes one PMOS transistor.
 6. The read data pathcircuit of claim 5, wherein the second conductive type precharging unitincludes two PMOS transistors.
 7. The read data path circuit of claim 4,wherein the precharging unit precharges the input/output lines to avoltage equal to an operation voltage of the semiconductor memory deviceminus a threshold voltage of the two NMOS transistors.
 8. The read datapath circuit of claim 1, further comprising: a half source voltageprecharging/equalizing unit configured to precharge the input/outputlines to a voltage equal to half of a source voltage until a word lineis activated.
 9. The read data path circuit of claim 8, wherein the halfsource voltage precharging/equalizing unit includes NMOS transistors.10. The read data path circuit of claim 1, wherein the precharging unitprecharges the input/output lines to a voltage equal to an operationvoltage of the semiconductor memory device.
 11. A semiconductor memorydevice comprising: a memory cell array including a plurality of memorycells arranged in a matrix, each of the plurality of memory cellsincluding at least one access transistor and one storage capacitor; aplurality of first sense amplifiers electrically connected tocorresponding bit lines electrically connected to the plurality ofmemory cells; a plurality of precharging units each of which includes afirst conductive type precharging unit, a second conductive typeprecharging unit and an equalizing unit, the first conductive typeprecharging unit configured to precharge first input/output lines, theequalizing unit configured to equalize a voltage of the firstinput/output lines, the second conductive type precharging unitconfigured to precharge the first input/output lines following anelapsed time after a associated first sense amplifier of the pluralityof first sense amplifiers is activated and while an associated columnselecting unit of a plurality of column selecting units is deactivated.12. The semiconductor memory device of claim 11, wherein, each of theplurality of column selecting units is configured to operationallyconnect the bit lines to the first input/output lines in response to aselection signal, and second input/output lines electrically connect oneof a corresponding plurality of second sense amplifiers to a third senseamplifier.
 13. The semiconductor memory device of claim 11, wherein, ifthe first conductive type precharging unit includes NMOS transistors,the second conductive type precharging unit includes PMOS transistors.14. The semiconductor memory device of claim 13, further comprising: aplurality of half source voltage precharging/equalizing units configuredto precharge the input/output lines to a voltage equal to half of asource voltage until a corresponding word line is activated.
 15. Thesemiconductor memory device of claim 14, wherein each of the pluralityof half source voltage precharging/equalizing units includes NMOStransistors.
 16. The semiconductor memory device of claim 11, whereineach of the plurality of precharging units includes, a delay unitconfigured to delay an enable signal to a corresponding sense amplifierof the plurality of second sense amplifiers; and a NAND gate performinga NAND operation on an output of the delay unit and an equalizationenable signal of the equalizing unit, to produce a NAND response inorder to activate the second conductive type precharging unit.
 17. Thesemiconductor memory device of claim 11, wherein the plurality ofprecharging units precharge the first input/output lines to a voltageequal to an operation voltage of the memory cell array.
 18. A read datapath circuit of a semiconductor memory device, the circuit comprising: afirst sense amplifier; a second sense amplifier; a column selecting unitconfigured to operationally connect bit lines corresponding to the firstsense amplifier to input/output lines corresponding to the second senseamplifier, in response to a selection signal; and a precharging unitconfigured to precharge the input/output lines by NMOS transistors, theprecharging unit configured to equalize a voltage of the input/outputlines by a PMOS transistor, and the precharging unit configured toprecharge the input/output lines by PMOS transistors following anelapsed time after the first sense amplifier is activated and theselection signal is deactivated.
 19. The read data path circuit of claim18, wherein the precharging unit includes, a delay unit configured todelay an enable signal to the second sense amplifier; and a NAND gateperforming a NAND operation on an output of the delay unit and anequalization enable signal of the PMOS transistor for equalizing, toproduce a NAND response in order to activate the second conductive typeprecharging unit.
 20. The read data path circuit of claim 18, furthercomprising: a half source voltage precharging/equalizing unit configuredto precharge the input/output lines to half of a source voltage until aword line is activated.